Researchers from the University of California, Riverside (UCR) are working diligently to enhance the speed and efficiency of hardware devices through a process known as simultaneous and heterogeneous multithreading (SHMT).
With the rise of modern hardware, like phones and computers, the need for multiple processors is more evident than ever. These devices often depend on a variety of processors, including a graphics processing unit (GPU), a central processing unit (CPU), and in some cases, a tensor processing unit (TPU) for machine learning tasks.
Maximizing Processor Use with SHMT
SHMT seeks to efficiently utilize all the processors in a device for improved performance. Its primary goal is to reduce the data bottlenecks that can occur when different units are transferring data among themselves. By performing more subtasks at the same time across the processors, these slowdowns can be minimized.
The Test Setup’s Results
The researchers' test setup demonstrated promising results. The execution of sample code using the SHMT model was nearly twice as fast, and the energy consumption was cut by 51 percent.
Overcoming Current Programming Limitations
Current programming models have a tendency to focus on using the most efficient processing units for each code region, often leaving much of the processing power underutilized. SHMT presents a potential solution to this problem.
The Challenges of SHMT
Despite the promising potential of SHMT, there are still obstacles to overcome. One challenge is the effective splitting of computing jobs to be processed by different types of processors. The ideal situation is to carry out the division of tasks without causing any slowdown in the system's performance.
Precision and Quality Assurance
Furthermore, the SHMT model must guarantee quality as the underlying architectures may have potential precision mismatches. Therefore, maintaining quality is a significant aspect of this research.
Research Presentation
UCR researchers presented their research on SHMT at the 56th Annual IEEE/ACM International Symposium on Microarchitecture in Toronto, Canada.